Multilayer MoS2 Back-Gate Transistors with ZrO2 Dielectric Layer Optimization for Low-Power Electronics
| Author(s) | Zhao, Haochen | |
| Author(s) | Lin, Guangyang | |
| Author(s) | Cui, Peng | |
| Author(s) | Zhang, Jie | |
| Author(s) | Zeng, Yuping | |
| Date Accessioned | 2022-03-30T18:12:16Z | |
| Date Available | 2022-03-30T18:12:16Z | |
| Publication Date | 2022-02-18 | |
| Description | This is the peer reviewed version of the following article: Zhao, H., Lin, G., Cui, P., Zhang, J. and Zeng, Y. (2022), Multilayer MoS2 Back-Gate Transistors with ZrO2 Dielectric Layer Optimization for Low-Power Electronics. Phys. Status Solidi A 2100760. https://doi.org/10.1002/pssa.202100760, which has been published in final form at https://doi.org/10.1002/pssa.202100760. This article may be used for non-commercial purposes in accordance with Wiley Terms and Conditions for Use of Self-Archived Versions. This article may not be enhanced, enriched or otherwise transformed into a derivative work, without express permission from Wiley or by statutory rights under applicable legislation. Copyright notices must not be removed, obscured or modified. The article must be linked to Wiley’s version of record on Wiley Online Library and any embedding, framing or otherwise making available the article or pages thereof by third parties from platforms, services and websites other than Wiley Online Library must be prohibited. This article will be embargoed until 02/18/2023. | en_US |
| Abstract | Herein, high-performance back-gate molybdenum disulfide (MoS2) field-effect transistors (FETs) with high-quality sub-20 nm high-k dielectric layers are developed for high-performance and lower-power consumption applications. The 20 nm ultrathin ZrO2 dielectric layers are deposited by thermal atomic layer deposition (ALD) method, where the growth temperature is varied and it shows a significant impact on the electrical characteristics of the deposited ZrO2 materials. A polydimethylsiloxane (PDMS) transfer process is used to transfer multilayer MoS2 flakes onto a 20 nm ZrO2/p–Si substrate with an optimized dielectric growth temperature without any subsequent processing, resulting in back-gate MoS2 FET device architecture. These transistors demonstrate excellent electrical characteristics with on–off current ratio up to 1.8 × 107, subthreshold swing as low as 70 mV decade−1 and field-effect mobility as high as 3.9 cm2 V−1 s−1. Furthermore, an enhancement-mode device operation and a high complementary metal–oxide–semiconductor (CMOS) ION/IOFF ratio of 107 are achieved. The excellent electrical performance is attributed to the low interface state traps and high-quality ZrO2 dielectric layer, indicating the great potential of our multilayer MoS2 FETs technology for low-power applications. | en_US |
| Sponsor | This work was supported in part by the NASA International Space Station under Grant 80NSSC20M0142, and in part by Air Force Office of Scientific research under Grant FA9550-19-1-0297 and Grant FA9550-21-1-0076. | en_US |
| Citation | Zhao, H., Lin, G., Cui, P., Zhang, J. and Zeng, Y. (2022), Multilayer MoS2 Back-Gate Transistors with ZrO2 Dielectric Layer Optimization for Low-Power Electronics. Phys. Status Solidi A 2100760. https://doi.org/10.1002/pssa.202100760 | en_US |
| ISSN | 1862-6319 | |
| URL | https://udspace.udel.edu/handle/19716/30739 | |
| Language | en_US | en_US |
| Publisher | physica status solidi (a) | en_US |
| Keywords | multilayer back-gate MoS2 transistor | en_US |
| Keywords | PDMS transfer | en_US |
| Keywords | threshold voltage and lower power electronics | en_US |
| Keywords | ZrO2 | en_US |
| Keywords | CMOS \ON/\OFF ratio | en_US |
| Title | Multilayer MoS2 Back-Gate Transistors with ZrO2 Dielectric Layer Optimization for Low-Power Electronics | en_US |
| Type | Article | en_US |
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