Tower methodology for verification of multi-core architecture: a case study
Date
2005
Authors
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Publisher
University of Delaware
Abstract
The creation of a computer system has become a monumental task. Many designers, engineers, and scientists cooperate to create the computer system down to its most basic components. An extremely crucial phase of the design of the hardware sub-systems is the verification of the hardware paradigms and structures that will work in synch to create the new computer system. Therefore, the verification of a system level chip is quite a complex task. Moreover, the verification process in any design is considered a major bottleneck, but it is required to ensure that the number of errors in the hardware designs is minimized. It can be safely said that the complexity of verification increases exponentially with the increase in design complexity [1]. There is definitely a need to use more than one verification tool to test a system-level chip design. Various ‘System on Chip’ verification methodologies have been developed and are being used in the market. However, these methodologies require anywhere from a medium to a large amount of resources and complex verification structures. A two-level verification methodology has been proposed in this thesis for the multi-core architecture of Cyclops-64, which involves a significant amount of resources. Moreover, it has enough functionality to compete with system level verification methodologies that are available in the market. The Two-Level Verification method involves the classic functional verification and the software emulation. This thesis demonstrates the application of the two level verification methodologies to the inter-processor communication module of the Cyclops 64 architecture. ☐ The bottom-up verification methodology proves to be a very efficient in term of reusability of the test-benches, groups of programs and/or data that is used for verifying the system. Thus, this methodology was a logical choice for the Functional Verification part of the two-level verification process. Functional verification can be carried out with any hardware simulation tool available, like Modelsim. This type of verification helps in acquiring a detailed knowledge of the system components. At the same time, it makes it possible to perform extensive verification on each of these components. The complexity of a system level design calls for the use (or the creation) of a robust and automatized tool set. Usually, existent tools and a small set of “glue” programs (i.e. programs that will coordinate between different parts of the tool) form such tool sets. The methodology that is being proposed by this thesis will use the above formula. Software emulation provides a set of robust and automatized programs and tools. A typical software emulation tool has a code generator, which is used to convert the component’s code written in a hardware description language to a gate level instruction code in ‘C’; a logical processor, which emulates the component and an automatic test pattern generator; and an output checker to avoid any manual error in verification. This thesis demonstrates the • 1. Functional verification for the inter-processor communication module (A-Switch) of the Cyclops 64 architecture. • 2. Application of the second level verification methodology-software emulation to the A-Switch module. • 3. Combination of the two levels for a full system level verification. • 4. Preliminary verification of the A-Switch.