System protoyping and thermal modeling of IR LED projectors including wafer-bonded superlattice light emitting diodes on GaAs

Abstract

Infrared scene projectors (IR SPs) are critical laboratory tools in the setup, testing and calibration of infrared imaging systems. These projectors stimulate the entire sensor system with a test scenario to create an infrared scene of precisely known characteristics, providing a high level of testing fidelity. ☐ Current IR projectors cannot stimulate appropriate prototype scenes for current IR sensors due to the growing gap between the sensor array sizes, which now exceed tens of millions of pixels, and the resolution and dynamic range capacity of infrared projectors, which typically remains below one megapixel. ☐ Infrared superlattice light emitting diode (IR SLED) arrays represent a potentially game-changing technology for presenting infrared images in sensor ground test environments, offering high frame rates and high temperature simulation while achieving superior manufacturing yield and greater uniformity than provided by competing resistor array technology. IR SLED technology has quickly advanced from use in semiconductor physics research to become an integral part of complete scene projector systems with a performance potential that exceeds that of micro-emitter arrays. ☐ With the goal of improving resolution and performance level, several generations of IR SLED projectors have been developed for hardware-in-the-loop testing. These projectors use an array of SLEDs hybridized with a read-in integrated circuit (RIIC) driven by various electrical components that are controlled by a field-programmable gate array (FPGA). ☐ To project high apparent temperatures and accurate IR scenes, the temperature increase within the active layer of the IR SLED array and the transistor at the RIIC must be minimized. Thermal models of single pixels, sub-arrays and hybridized full arrays are used to guide the design process. Results from these modeling efforts are also used to estimate the operating limits and thermal time constants of the arrays and to develop the tools necessary to incorporate a real-time non-uniformity correction (NUC) procedure in the IR scene generators. ☐ Typically, the SLED arrays are mated with complementary metal-oxide semiconductor (CMOS) RIIC chips via flip-chip bonding. An alternative approach where IR SLED wafers are wafer bonded to GaAs RIIC wafers is proposed. This processing technique provides significant cost reduction, as well as improved thermal management and radiation performance.