Browsing by Author "Zhao, Haochen"
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Item Fabrication of Germanium Tin Microstructures Through Inductively Coupled Plasma Dry Etching(IEEE Transactions on Nanotechnology, 2021-09-30) Lin, Guangyang; Cui, Peng; Wang, Tao; Hickey, Ryan; Zhang, Jie; Zhao, Haochen; Kolodzey, James; Zeng, YupingGermanium tin (GeSn) with a Sn content of >12% has a great potential for optoelectronic devices due to its direct bandgap property. In this work, the anisotropic etching of GeSn with Sn content of 12.5% and selective etching of Ge over GeSn were explored by inductively couple plasma (ICP) dry etching to obtain various microstructures. Through adding oxygen into chlorine and argon and adjusting the process pressure, the anisotropic etching of GeSn was optimized with an ideal sidewall angle of 89 o . The optimized process is compatible with both positive and negative resists. By altering the ICP power, Ge etching recipes with low and high etching rates were developed, which are favorable for fabricating GeSn nano- and micro-structures, respectively. An etching selectivity of >126 for Ge over GeSn with Sn content of >10% can be achieved. With the optimized dry etching recipes, suspended GeSn microribbons and microdisks were realized. Ultimately, the suspended GeSn microstructures were transferred onto 40-nm-thick ZrO 2 on p + -Si to form a GeSn-on-insulator (GeSnOI) substrate. For a fabricated 45-nm-thick Ge 0.875 Sn 0.125 OI back-gated transistor, the subthreshold swing (SS) of 240 mV/dec is reasonably low for a non-optimized device, suggesting that the explored dry etching methods are promising for device processing.Item Multilayer MoS2 Back-Gate Transistors with ZrO2 Dielectric Layer Optimization for Low-Power Electronics(physica status solidi (a), 2022-02-18) Zhao, Haochen; Lin, Guangyang; Cui, Peng; Zhang, Jie; Zeng, YupingHerein, high-performance back-gate molybdenum disulfide (MoS2) field-effect transistors (FETs) with high-quality sub-20 nm high-k dielectric layers are developed for high-performance and lower-power consumption applications. The 20 nm ultrathin ZrO2 dielectric layers are deposited by thermal atomic layer deposition (ALD) method, where the growth temperature is varied and it shows a significant impact on the electrical characteristics of the deposited ZrO2 materials. A polydimethylsiloxane (PDMS) transfer process is used to transfer multilayer MoS2 flakes onto a 20 nm ZrO2/p–Si substrate with an optimized dielectric growth temperature without any subsequent processing, resulting in back-gate MoS2 FET device architecture. These transistors demonstrate excellent electrical characteristics with on–off current ratio up to 1.8 × 107, subthreshold swing as low as 70 mV decade−1 and field-effect mobility as high as 3.9 cm2 V−1 s−1. Furthermore, an enhancement-mode device operation and a high complementary metal–oxide–semiconductor (CMOS) ION/IOFF ratio of 107 are achieved. The excellent electrical performance is attributed to the low interface state traps and high-quality ZrO2 dielectric layer, indicating the great potential of our multilayer MoS2 FETs technology for low-power applications.