LC-Sim: a simulation framework for evaluating location consistency based cache protocols
| Author(s) | Fotouhi, Pouya | |
| Date Accessioned | 2018-01-23T12:58:34Z | |
| Date Available | 2018-01-23T12:58:34Z | |
| Publication Date | 2017 | |
| SWORD Update | 2017-09-05T16:31:11Z | |
| Abstract | New high-performance processors tend to shift from multi to many cores. More- over, shared memory has turned to dominant paradigm for mainstream multicore pro- cessors. As memory wall issue loomed over architecture design, most modern computer systems have several layers in their memory hierarchy. Among many, caches has be- come everlasting components of memory hierarchies as they signicantly reduce access time by taking the advantage of locality. ☐ Major processor vendors usually rely on cache coherence, and implement a vari- ant of MESI, e.g., MOESI for AMD, to help reduce inter-chip trac on the fast in- terconnection network. Supposedly, maintaining coherence should help with keeping parallel and concurrent programmers happy, all the while providing them with a well- known cache behavior for shared memory. This thesis challenge the assumption that Coherence is well-suited for large-scale many core processors. Seeking an alternative for coherence, LC cache protocol is extensively investigated. ☐ LC-Cache is a cache protocol weaker than Coherence, but which preserves causality. It relies on the Location Consistency (LC) model. The basic philosophy behind LC is to maintain a unique view of memory only if there is a reason to. Other ordinary memory accesses may be observed in any order by the other processors of the computer system. ☐ The motivation to stand against cache coherence, relies on underestimated lim- itations implied on system design by coherence. Observations presented in this thesis, demonstrates that coherence eliminates the possibility of having a directory based pro- tocol in practice since size of such directory grows linearly with number of cores. In addition, coherence adds implicit latency in many cases to the protocol. ☐ This thesis presents LCCSim, a simulation framework to compare cache proto- col based on location consistency against cache coherence protocols. A comparative analysis between the MESI and MOESI coherence protocols is provided, and pit them against LC-Cache. Both MESI and MOESI consistently generate more on-chip trac compared to LC cache since transitions in LC cache are done locally. However, LC cache degrades total latency of accesses as it does not take the advantage of cache to cache forwarding. Additionally, LC cache cannot be considered a true implementation based on LC since it does not behave according to the memory model. The following summarizes the contributions of this thesis: 1.Detailed specication of LC cache protocol, covering the missing aspects in the original paper. 2.A simulation framework to compare cache protocols based on LC against cache coherence protocols. 3.Extensive analysis of LC cache protocol, leading to discovery of several weak- nesses. 4.Demonstrating features for an ecient cache protocol, truly based on location consistency. | en_US |
| Advisor | Gao, Guang R. | |
| Degree | M.S. | |
| Department | University of Delaware, Department of Electrical and Computer Engineering | |
| Unique Identifier | 1020169925 | |
| URL | http://udspace.udel.edu/handle/19716/22607 | |
| Language | en | |
| Publisher | University of Delaware | en_US |
| URI | https://search.proquest.com/docview/1975368783?accountid=10457 | |
| Keywords | Applied sciences | en_US |
| Keywords | Cache protocol | en_US |
| Keywords | Exa-scale | en_US |
| Keywords | Location consistency | en_US |
| Keywords | Memory consistency model | en_US |
| Title | LC-Sim: a simulation framework for evaluating location consistency based cache protocols | en_US |
| Type | Thesis | en_US |