Reconfiguration optimization for nonvolatile memories based field programmable gate arrays
Date
2018
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
University of Delaware
Abstract
Field Programmable Gate Arrays (FPGAs) are programmable logic blocks based circuit
devices, which can be configured to different logic functions due to various demands.
Compared with application-specific integrated circuits (ASICs), FPGAs are able to deliver
much lower non-recurring engineering costs and much shorter time-to-market of product. As
time goes by, the popularity of FPGAs increases due to the super flexibility of configurable
soft logic. The recent trends toward wide appliance of the coarse-grained architectural approach
that combines FPGAs with microprocessors cores and uses FPGAs as accelerators or
co-processors, make FPGAs even more indispensable. ☐ Traditionally the manufacturing of FPGAs is based on static random-access memory
(SRAMs) technology. As the transistor feature size goes down to the deep-nano scale (less
than 20nm), the drawbacks of SRAM are exposed explicitly such as high leakage power and
limited scalability. SRAMs are also unreliable since the logic information would be lost if
the power supply is off. ☐ Non-volatile memories (NVMs) outperform traditional SRAMs regarding low power
consumption, high capacity, near-zero power-on delay, and high error-resistance. Researchers
have demonstrated the possibilities of implementing FPGA building blocks with various
types of NVMs. However, using NVMs also brings several new design challenges to FPGAs:
the slow and energy-hungry write operations of NVM may degrade FPGA (re) configuration
speed and power efficiency, while the limited write endurance of NVM constrains the
number of times that the FPGA can be (re)configured, leading to quite short device lifetime.
Unfortunately, none of these NVM features is taken into consideration in current FPGA
synthesis flows, which are optimized solely for SRAM-FPGAs. To qualify NVM-FPGA deployment,
FPGA synthesis flow should be optimized and tuned to take NVM characteristics
into consideration. ☐ In this dissertation, to tackle the two aforementioned major NVM limitations, an
NVM friendly FPGA synthesis flow is elaborately developed. Particularly, logic synthesis,
placement, and routing stage are enhanced and optimized for being compatible with NVMFPGA.
In logic synthesis, the flip-flops (FFs), which can be built with NVM devices, are the
essential elements for finite state machine (FSM) construction. To efficiently use flip-flops
and reduce dynamic power caused by bit flips, an NVM-friendly state encoding framework
is proposed. Placement aims at configuring configurable logic blocks (CLBs) and consists
of co-placement and logic placement. First, an age-aware co-placement is taken to choose
the design area for memory blocks and logic blocks. Then, the logic placement with different
placement algorithms is executed to balance CLB reconfiguration cost and traditional
constraints such as timing. In routing, the reconfiguration costs of NVM-based switch boxes
(SBs) which are used for global routing and connection can be optimized. A routing path
reuse technique is proposed to reduce SB reconfiguration costs efficiently through a path
reuse maximization scheme together with a reuse-aware routing algorithm. ☐ The studies in this dissertation have the potentials in promoting the popularity and
practicality of NVM-FPGAs. The proposed research studies have the potentials in offering
energy-efficient, reliable, and long-lasting FPGAs for future generation of self-adaptive
systems.