Hardware and close support electronics architectures for enabling a packetized display protocol on IRLED scene projectors
Date
2021
Authors
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Publisher
University of Delaware
Abstract
Infrared (IR) imaging systems can characterize the unique IR signatures of high-temperature objects, making them extremely useful for various military, academic, and industrial applications. Infrared Scene Projectors (IRSP) are devices for simulating real-time IR scenes and allow the user to test and calibrate imaging systems in scenarios that would otherwise be impractical. In 2014, our research group created the first infrared light-emitting diode (IRLED) scene projector called Super-lattice Light Emitting Diode Systems (SLEDS). Since then, these systems have gone through several iterations, each generation increasing the resolution and frame-rates to keep up with consumer demands. IRLED scene projectors are used in hardware in the loop testing (HITL) to test real-time imaging systems with synthetic infrared imagery. ☐ Scene generators produce synthetic infrared imagery, which has historically been transmitted via traditional display protocols to be projected by the IRSP. Traditional display protocols have limitations in terms of high bandwidth requirements, fixed refresh-rates, and control over how frames are displayed. A novel packetized display protocol (PDP) is under development to expand display capabilities for intelligent bandwidth utilization, dynamic inter-frame and intra-frame (sub-window) frame-rates, increased performance, and eased synchronization burden. ☐ This research investigates the hardware necessary to enable PDP on IRLED scene projector systems and to interface with outside scene generator systems. A custom prototype printed circuit board to interface with the IRLED scene projector’s close support electronics (CSE) is presented. This board utilizes a field-programmable gate array (FPGA) and two input/output HDMI links. FPGAs are useful and powerful devices that can be reconfigured to meet the needs of the user. FPGAs perform highly parallel computations, potentially allowing for implementation and hardware acceleration of algorithms (such as non-uniformity correction) directly on the chip. This first prototype board uses HDMI as the transport medium for PDP to both maintain backward compatibility with prior SLEDs systems and to demonstrate how PDP can be implemented onto any physical data transfer link. ☐ This thesis describes the design and architecture of the next-generation CSE necessary to match future IRLED IRSP resolution and frame-rate demands. This architecture eschews the traditional display protocol hardware links for scene generation in favor of high-speed serial data connection, such as ethernet or fiber. Increased effective bandwidth due to elimination of video blanking periods allows the full potential of PDP the be demonstrated. Synchronization of the new generation CSE DACs through the JESD204B protocol is presented. Design considerations for a more robust third-generation distributed FPGA CSE are discussed.
Description
Keywords
FPGA, Infrared, IRLED, IRSP, Packetized display protocol, Scene projector