Tolerating Defects in Low-Power Neural Network Accelerators Via Retraining-Free Weight Approximation

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Author(s)Hosseini, Fateme S.
Author(s)Meng, Fanruo
Author(s)Yang, Chengmo
Author(s)Wen, Wujie
Author(s)Cammarota, Rosario
Date Accessioned2022-01-12T18:28:32Z
Date Available2022-01-12T18:28:32Z
Publication Date2021-09-23
DescriptionThis article was originally published in ACM Transactions on Embedded Computing Systems. The version of record is available at: https://doi.org/10.1145/3477016en_US
AbstractHardware accelerators are essential to the accommodation of ever-increasing Deep Neural Network (DNN) workloads on the resource-constrained embedded devices. While accelerators facilitate fast and energy-efficient DNN operations, their accuracy is threatened by faults in their on-chip and off-chip memories, where millions of DNN weights are held. The use of emerging Non-Volatile Memories (NVM) further exposes DNN accelerators to a non-negligible rate of permanent defects due to immature fabrication, limited endurance, and aging. To tolerate defects in NVM-based DNN accelerators, previous work either requires extra redundancy in hardware or performs defect-aware retraining, imposing significant overhead. In comparison, this paper proposes a set of algorithms that exploit the flexibility in setting the fault-free bits in weight memory to effectively approximate weight values, so as to mitigate defect-induced accuracy drop. These algorithms can be applied as a one-step solution when loading the weights to embedded devices. They only require trivial hardware support and impose negligible run-time overhead. Experiments on popular DNN models show that the proposed techniques successfully boost inference accuracy even in the face of elevated defect rates in the weight memory.en_US
CitationFateme S. Hosseini, Fanruo Meng, Chengmo Yang, Wujie Wen, and Rosario Cammarota. 2021. Tolerating Defects in Low-Power Neural Network Accelerators Via Retraining-Free Weight Approximation. ACM Trans. Embedd. Comput. Syst. 20, 5s, Article 85 (September 2021), 21 pages. https://doi.org/10.1145/3477016en_US
ISSN1558-3465
URLhttps://udspace.udel.edu/handle/19716/29964
Languageen_USen_US
PublisherACM Transactions on Embedded Computing Systemsen_US
KeywordsComputer systems organizationen_US
KeywordsReliabilityen_US
KeywordsNeural networksen_US
KeywordsEmbedded softwareen_US
KeywordsHardwareen_US
KeywordsError detectionen_US
Keywordserror correctionen_US
KeywordsNeural network acceleratoren_US
Keywordsdefect toleranceen_US
Keywordsmemory faultsen_US
Keywordsapproximationen_US
TitleTolerating Defects in Low-Power Neural Network Accelerators Via Retraining-Free Weight Approximationen_US
TypeArticleen_US
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