Design of a 9 stage 10 bit high speed pipeline analog to digital converter

Author(s)Long, Xi
Date Accessioned2011-06-02T12:12:59Z
Date Available2011-06-02T12:12:59Z
Publication Date2010
AbstractAnalog to digital converter (ADC) design has been an active research topic over the past few decades, as the scaling down of Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuit (IC) fabrication process offers continuing room for performance improvement. Various ADC architectures have been proposed by researchers, including flash, successive approximation, sigma-delta and pipeline, etc. Among these architectures, pipeline ADC offers moderate resolution at high conversion speed and is widely used in both civil and military applications. In this thesis, we develop a 9 stage 10 bit pipeline ADC circuit in AMIS C5N process. The whole design methodology, from system simulation to schematic entry, from circuit simulation to post signal analysis is proposed. The operation frequency of the pipeline ADC is pushed to the upper limit of the process used. The ADC is designed and simulated in Cadence environment. Post simulation signal analysis is done in Matlab in order to verify its performance.en_US
AdvisorGoossen, Keith W.
DegreeM.S.
DepartmentUniversity of Delaware, Department of Electrical and Computer Engineering
URLhttp://udspace.udel.edu/handle/19716/5947
PublisherUniversity of Delawareen_US
dc.subject.lcshAnalog-to-digital converters -- Design
dc.subject.lcshPipelining (Electronics) -- Design
TitleDesign of a 9 stage 10 bit high speed pipeline analog to digital converteren_US
TypeThesisen_US
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