Modeling and simulation of nano-scale transistor
Date
2022
Authors
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Journal ISSN
Volume Title
Publisher
University of Delaware
Abstract
Modeling and simulation of nano-scale transistor plays an important role in designing circuits. They serve as the medium of exchanging information between foundries and circuit designers. In the past several decades, the innovations of transistor technology such as FDSOI and FinFET have been the main driving force of semiconductor industry. As the node CD of modern transistor is shrinking down to sub-5 nm nowadays, novel device concept and new semiconductor material need new device model methodology and understanding of device physics. This dissertation presents the research on tunneling FET (TFET) and InAs MOSFET device models. ☐ For MOSFETs, the theorical limit of 60 mV/dec has posed an undesirably high-power consumption during the on/off switch. The high off-status leakage current causes problems for digital circuit applications. What’s more, short channel effects such as drain induced barrier lowering (DIBL) has also been a challenge for every iteration of technology node. ☐ Compared with MOSFETs, TFET is widely viewed as the promising candidates for future low-power logic/analog application Because of its steep subthreshold slope, better resistance to short channel effects, and high Ion/Ioff ratio. But the main drawback of existing TFET technology is the low on current. Because the on current of TFET is generated by the carrier’s band-to-band tunneling, the tunneling window and the length of tunneling path are modulated by the channel electric potential. Therefore, In the traditional lateral TFET, the main tunneling area is constrained in the region with higher electric potential. Recently, the line/vertical TFET structure has been proposed to solve this issue. Different from the lateral TFET, the whole channel of the vertical TFET can be the active band-to-band tunneling area. However, a compact/spice model that can predict vertical TFET’s performance and provide physical insights into its behavior is still lacked. ☐ The first objective of this dissertation is to develop a spice model for the vertical TFET. It starts with an analytical model for the electric potential. The electric potential formula is derived for the first time from the multi-branch general solutions of Poisson’s equation for TFETs. The effect of electron inversion charge in the channel is taken into account. A novel approach incorporating the effect of hole mobile charge in the source depletion region is proposed. The model’s accuracy is significantly improved compared with the previous source fully depleted approximation. ☐ Based on the above electric potential model, the Kane’s tunneling formula is utilized for the calculation of band-to-band tunneling current. The model is proven to be accurate in all operating regions. Unlike the 1-D tunneling approximation that has been widely used in the modeling area of lateral TFET, the surface electric potential at different position of the channel region is utilized to compute the tunneling current. The model’s results are verified with TCAD simulation for transistors with different structural parameters, material parameters, and biases. High accuracy of the proposed model has been proven in all operating regions. The analytical model shows much higher computational efficiency than the Synopsys Sentaurus TCAD simulator. ☐ The capacitance-voltage (CV) model is an essential for circuit design and radio-frequency (RF) simulations. Developing a CV model for vertical TFET involves different mechanisms and physics from the concept of MOSFET. In this work, the source depletion charge and channel inversion charge are considered for a vertical TFET. Due to the separation effect of the tunneling barrier, the source depletion charge is assigned to the source terminal, the channel inversion charge is assigned to the drain terminal. Their individual contributions to the capacitances are calculated by the Ward-Dutton approach. ☐ The second objective of this dissertation is to investigate the design strategy in the self-aligned InAs MOSFETs. A 2-D TCAD simulation is performed based on the experimental data of quantum-well transistor. The effect of air gap between the T-shaped metal contacts is taken into account. It is found that the fringing effects induced by the air gap has significant impacts on both DC and RF performances. Further study is carried out based on this TCAD simulation platform. The channel extension region, which is simply considered as part of series resistance, needs to be properly designed to maximize fT and fMAX. ☐ Following the similar approach, a benchmarking comparison between InAs FinFET and gate-all-around (GAA) MOSFET is demonstrated by a 3-D TCAD simulation. The complete FinFET fabrication process is demonstrated followed by a TCAD simulation platform based on the experimental data. Both DC and RF simulation results are shown here. Further optimizations are explored for InAs FinFET/GAA MOSFET through TCAD simulations. It is found that with optimizations in materials, device geometry and fabrication, significant enhancement in DC/RF performances is possible with these devices. In addition, GAA MOSFET shows a better potential for future RF application.
Description
Keywords
Compact model, Poisson's equation, TCAD stimulation, Tunneling FET