Toward high performance and energy efficiency on many-core architectures
Date
2014
Authors
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Publisher
University of Delaware
Abstract
The research proposed in this thesis will provide an analysis of these new scenarios, proposing new methodologies and solutions that leverage these new challenges in order to increase the performance and energy efficiency of modern many-core architectures. During the pursue of these objectives, this research intends to answer the following question: 1. Which is the impact of low-level compiler transformations such as tiling and percolation to effectively produce high performance code for many-core architectures? 2. What are the tradeoffs of static and dynamic scheduling techniques to efficiently schedule fine grain tasks with hundreds of threads sharing multiple resources under different conditions in a single chip? 3. Which hardware architecture features can contribute to better scalability and higher performance of scheduling techniques on many-core architectures on a single-chip? 4. How to effectively model high performance programs on many-core architectures under resource coordination conditions? 5. How to efficiently model energy consumption on many-cores managing tradeoffs between scalability and accuracy? 6. Which are feasible methodologies for designing power-aware tiling transformations on many-core architectures? (Abstract shortened by UMI.)